--叶佳豪 201841052073
--100进制 BCD码加法计数器 年计数器
--***************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*************************************************
ENTITY COUNT_YEAR IS
    PORT(
			CLK,CLR		:IN STD_LOGIC;
			Q 			:OUT STD_LOGIC_vector(15 downto 0);
			TCN			:OUT STD_LOGIC
		);
END COUNT_YEAR;
--**************************************************
ARCHITECTURE RUN OF COUNT_YEAR IS
SIGNAL Q12 : std_logic_vector(7 downto 0):="00100000";
SIGNAL Q34 : std_logic_vector(7 downto 0):="00000000";
SIGNAL TTCN 	:STD_LOGIC;
BEGIN
	P_Q34:PROCESS(CLK,CLR)
	BEGIN
		IF CLR = '0' THEN Q34 <= "00000000";
		ELSIF CLK'EVENT AND CLK = '1' THEN
			TTCN<= '0';
			IF Q34 >= "10011001" THEN Q34 <= "00000000";TTCN<='1';		--99复位
			ELSIF Q34(3 downto 0) >= "1001" THEN						--十位进位
				Q34(3 downto 0) <= "0000";
				Q34(7 downto 4) <= Q34(7 downto 4) + 1;
			ELSE Q34 <= Q34 + 1;							--个位进位
			END IF;
		END IF;

	END PROCESS;
	P_Q12:PROCESS(TTCN,CLR)
	BEGIN
		IF CLR = '0' THEN Q12 <= "00000000";
		ELSIF TTCN'EVENT AND TTCN = '1' THEN
			IF Q12 >= "10011001" THEN Q12 <= "00000000";TCN<='1';		--99复位
			ELSIF Q12(3 downto 0) >= "1001" THEN							--十位进位
				Q12(3 downto 0) <= "0000";
				Q12(7 downto 4) <= Q12(7 downto 4) + 1;
			ELSE Q12 <= Q12 + 1;							--个位进位
			END IF;
		END IF;
		
	END PROCESS;
Q(15 downto 8) <= Q12;Q(7 downto 0) <= Q34;
END RUN;
	
